Track and hold circuit

ABSTRACT

A track and hold system for use with a test instrument such as a multimeter includes an input circuit, a buffer amplifier, a storage device such as a capacitor, an output amplifier, an output circuit, a detector for detecting a pulse on a signal passing from the input to the output, and a switch responsive to the detector for isolating the storage device from the input circuit but not the output circuit for a predetermined period. The system also includes a timer responsive to the detector to provide an isolation command to the switch for the predetermined period. Further, the system includes a delay circuit, responsive to the detector, for interposing a delay of variable duration prior to activating the timer. In a preferred embodiment, where the system is used in conjunction with a multimeter having a &#34;hold&#34; circuit which directs the meter to display the last-measured signal, an output is provided to the hold input of the meter directing the meter to &#34;hold&#34; for predetermined periods whenever the switch opens or closes. The &#34;hold&#34; output circuit is also used to provide indefinite retention of a reading and trigger lockout for the detector circuitry.

BACKGROUND OF THE INVENTION

The present invention is a track and hold circuit for use in conjunctionwith electrical measuring equipment, such as multimeters.

A wide variety of electronic equipment in use today uses or generatespulses to activate or deactivate other circuitry or mechanisms. In manycases, it is important that the pulse have certain characteristics, suchas a particular amplitude and width. In the field, service personnelhave generally tested for the presence of such pulses by looking on ananalog meter for a "tick" in the measured quantity (a slight dip or riseon the pointer). Such a technique is unreliable and inaccurate, andgives no information about pulse characteristics. Without anoscilloscope or other expensive and bulky instrument, thecharacteristics of the pulse remain essentially unkown.

Accordingly, the principal object of the present invention is to providea device to adapt a multimeter to measure pulse profile.

It is a further object to provide a track and hold capability at minimumpower consumption so that essentially shelf-life of an ordinary 9Vbattery will be achieved, i.e. current <0.1 milliamper.

SUMMARY OF THE INVENTION

These and other objects are achieved by providing an input circuit forreceiving an input signal, a storage device connected to the inputcircuit for storing a signal corresponding to the instantaneous value ofthe amplitude of a pulse applied to the input circuit, an output circuitreceiving the output of the storage device, a pulse detector fordetecting a pulse, and a switching circuit connected to the pulsedetector to isolate the storage device from the input so that the outputsignal represents the amplitude of the pulse. In the preferredembodiment the pulse detector is connected to monitor the outputcircuit. The preferred embodiment also includes a delay circuit forinterposing a delay of selectable duration prior to activating theswitching circuit and means for selecting the duration of such delay.When a delay of zero duration is selected, the signal on the storagedevice corresponds to the initial pulse amplitude. When a delay oflarger duration is selected, the signal corresponding to initial pulseamplitude will have passed from the storage device to the output circuitwhen the switching circuit is activated; the signal on the storagedevice when the switching circuit is activated corresponds to the pulseamplitude at the selected delay time after the leading edge. Hence, thepulse amplitude at any position from the leading edge forward can beisolated so that the entire pulse profile may be measured.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention will bemore apparent from the following description which refers to theaccompanying drawings, wherein:

FIG. 1 is a block diagram showing the major operating components of thetrack and hold system according to the present invention;

FIG. 2 are timing diagrams of various representative signals occurringin the apparatus of FIG. 1; and

FIG. 3(a) is a more detailed circuit diagram of the apparatus shown inFIG. 1, further including a bypass switch to bypass the delay circuit 18shown in FIG. 1 and FIG. 3(b) is a circuit diagram of a power supply ofFIG. 3(a).

DESCRIPTION OF A PREFERRED EMBODIMENT

Referring to FIG. 1, an input terminal 10 receives an unknown analogsignal and applies such signal through the voltage divider formed byresistors R₁ and R₂ to the input of buffer amplifier A₁. The output ofamplifier A₁ is applied through a normally closed switch S₁ to a firstside of capacitor C₁, the second side of which is grounded. Capacitor C₁is driven by the low impedance of A₁ so that the voltage across itfollows the output of amplifier A₁. A slight lag is minimized byselecting an appropriate value for capacitor C₁. The first side ofcapacitor C₁ is connected to the input of output amplifier A₂, theoutput of which is applied to output terminal 14. An attenuated outputis taken from the junction of the voltage divider formed by resistorsR₁₈ and R₁₉ and applied to output terminal 16.

A pulse detecting circuit 17 is connected to the output of amplifier A₂.Pulse detection circuit 17 detects voltage rises which have apreselected rate of increase appearing at the output of amplifier A₂ andprovides a trigger signal coincident with the leading edge of such apulse. The trigger signal is applied to a delay circuit 18 whichprovides a delay of selectable duration after which it applies a signalto timer 20. In response thereto, timer 20 generates an output for apredetermined period which opens switch S₁. Switch S₁ thereby isolatescapacitor C₁ from the signal applied to input terminal 10. In this mode,the system provides an essentially constant amplitude output at output14 corresponding to the last value of the analog input stored incapacitor C₁. This mode is of sufficient duration so that a testinstrument such as a multimeter can measure the initial amplitude of apulse detected by the track and hold system. By varying the delay ofcircuit 18, the entire pulse profile may be measured, as set forthabove.

Certain test instruments such as the WESTON® DMM 6000 are provided witha "hold" mechanism or input whereby the multimeter will hold the readoutof the unknown measured immediately prior to the hold command. The"hold" signal can be used to prevent incorrect, partial amplitudereadings being displayed by the multimeter. The preferred embodiment ofthe present invention provides such a hold command to the input terminalof the test instrument. Hold circuit 22 receives an input from timer 20and applies a hold command for a predetermined period, illustratively200 milliseconds, to hold output 24 which, in use, is connected to thehold input of the associated meter. Additionally, hold circuit 22includes an autohold facility which is described below.

The operation of the circuit is best understood by refering to FIGS. 1and 2. As shown in FIG 2(a), a signal is applied to input terminal 10 ofthe track and hold system. The baseline signal may be a DC voltage or aslowly varying AC voltage, or a combination thereof. This signal isapplied to output terminal 14 while the system tracks the applied inputsignal. A pulse as shown in FIG. 2(a) appears on Capacitor C₁ as shownin FIG. 2(b). When the leading edge of that pulse on capacitor C₁ isencountered by the pulse detecting circuit 17, a trigger signal inresponse thereto is applied to delay circuit 18. Initially, the delaycircuit 18 is set to interpose no delay, and accordingly, timer 20 isactivated as soon as the leading edge of the pulse is detected. (In themore detailed circuit diagram of FIG. 3, the trigger signal isselectively applied by a switch to either delay 18 or timer 20.) Inresponse to the trigger signal, timer 20 opens switch S₁ for apreselected period, for instance 1500 millliseconds. Accordingly, thevoltage at output terminal 14 as shown in FIG. 2(c) corresponds to theinitial pulse amplitude, since a voltage representative thereof remainson capacitor C₁. This output endures for 1500 milliseconds, providing asufficient time for a meter to take a measurement.

Simultaneously with the opening of switch S₁, timer 20 applies a signalto hold circuit 22 which applies a hold command to hold output 24 for aperiod illustratively of 200 milliseconds as shown in FIG. 2(d). Output24 is normally held at a voltage of one or two volts, and is dropped tozero volts for the hold signal. A second hold command is applied to holdoutput 24 by hold circuit 22 when switch S₁ is closed at the end of the1500 millisecond period. The hold signal applied by hold circuit 22 tooutput 24 directs the associated meter to retain the previously measuredquantity on its display (while continuing to measure new unknowns).Otherwise a voltage intermediate the baseline and maximum of V₁₄ (FIG.2(c)), i.e., a voltage on the leading or trailing ramp, might bedisplayed. Such hold commands therefore ensure that the associatedmasuring instrument has a full measurement cycle for sensing orintegrating the applied unknown and that intermediate voltages are notdisplayed.

Additionally, the preferred embodiment of the present invention includesan autohold facility of hold circuit 22 which applies a hold command of200 milliseconds, illustratively, at the beginning of the 1500millisecond switch opening and an openend hold command as shown in FIG.2(e) when the switch S₁ is closed. This allows a user of the meter toreset or release the meter hold manually, which is particularly usefulwhen the user is not in a position to read the meter at once.

The track and hold circuit according to the invention cooperates with ameasuring instrument to determine the pulse amplitude at any desiredpoint on a pulse and its pulse width by selecting the delay time ofdelay circuit 18. The delay period is measured after the pulse leadingedge, so that the voltage on capacitor C₁ after the switch S₁ openscorresponds to pulse amplitude at any time of interest. As the delay isincreased gradually from zero, the meter continues to measure pulseamplitude. Ultimately, the duration of the delay will be set at a timeperiod which exceeds the duration of the pulse applied to input 10. Atsuch time, the meter will register zero or the baseline voltage. Thepulse width can be determined by observing the minimum delay time whichexceeds the pulse duration. Accordingly, the entire pulse profile may bedetermined.

A further feature of the preferred embodiment track and hold circuit ofthe present invention is an "inhibit" connection 28 between hold circuit22 and delay circuit 18. This connection is particularly useful whenpulse width measurements are being taken on one of a train of pulses.Absent such an "inhibit" connection, inaccurate readings may be made.For example, when one pulse is detected, switch S₁ is openedillustratively for 1500 milliseconds in response thereto. When switch S₁closes, an intermediate pulse characteristic of a subsequent pulse maybe falsely interpreted by pulse detection circuit 17 as the start of anew pulse rather than an intermediate characteristic. Accordingly, an"inhibit" signal of 200 milliseconds is provided when switch S₁ closesto disable delay circuit 18, so that no new opening of switch S₁ canoccur immediately.

As shown in the more detailed circuit diagram of FIG. 3(a), an inputapplied to input terminal 10 is connected through a voltage dividerformed by series resistors R₁ and R₂ to the non-inverting input ofbuffer amplifier A₁, a standard type 776 operational amplifier made byFairchild Semiconductor, for example. The output 50 of amplifier A₁ isfed back to its inverting input by conductor 52 to provide a unityvoltage gain characteristic.

The output 50 of amplifier A₁ is applied to the source of field effecttransistor Q₁, which constitutes switch S₁ of FIG. 1. The drain of FETQ₁ is connected to one side of a non-polar capacitor C₁. The other sideof capacitor C₁ is grounded.

The ungrounded side of capacitor C₁ is connected also to thenon-inverting input of amplifier A₂, also a 776 type operationalamplifier. The output 60 of amplifier A₂ is fed back to its invertinginput through the voltage divider formed by resistors R₄ and R₅, withresistor R₅ connected between output 60 of amplifier A₂ and theinverting input, and R₄ connected between the inverting input andground. The output 60 of amplifier A₂ is connected to output terminal14. Output 60 is connected also to both the upper contact 62 of a firstside of a double-pole double-throw polarity switch S₂ and to the lowercontact 64 of the second side of S₂. Both the lower contact 66 of thefirst side and the upper contact 68 of the second side of switch S₂ areconnected to ground. The blade 70 of the first side of S₂ is connectedthrough resistor R₇ and series capacitor C₂ to the inverting input oftrigger amplifier A₃, illustratively a 776 type operational amplifier.The blade 72 of the second side of S₂ is connected to the non-invertinginput of trigger amplifier A₃. The output 78 of amplifier A₃ is fed backto its inverting input through resistor R₈ which is connected parallelto diode D₁, the cathode of which is connected to output 78 and theanode of which is connected to the inverting input.

The output 78 of amplifier A₃ is connected to the anode of diode D₂, thecathode of which is connected by conductor 80 to the clock input C of aD-type flip-flop 180, illustratively one-half of a NationalSemiconductor 74C74. Resistor R₁₀ is connected between the cathode ofdiode D₂ and ground. The Q output of flip-flop 180 is connected to theanode of diode D₃, the cathode of which is applied to the "clear" input"Clr" of flip-flop 180. Variable resistor R₁₁ is connected parallel toD₃. In the preferred embodiment, resistor R₁₁ is a potentiometer havingits shaft extending out of the casing of the track and hold system.Surrounding the shaft and on the casing is a scale calibrated inmilliseconds. A suitable pointer-knob is affixed to the potentiometer sothat the scale is correlated to the value of resistance R₁₁ and,therefore, as explained below, the delay time interposed by the delaycircuit using flip-flop 180. The clear input is connected to one side ofcapacitor C₃, the other side of which is connected to ground.

Circuit 80 is connected to one contact 82 of single-pole double-throwby-pass switch S₃. The Q output of flip-flop 180 is connected to thesecond contact 84 of switch S₃. The blade 86 of switch S₃ is connectedto the clock input C of flip-flop 200, also a D-type and, conveniently,the second half of the 74C74.

Hence, switch S₃ operates as a selector or by-pass switch, either toconnect flip-flop 180 to or isolate flip-flop 180 from flip-flop 200.Flip-flop 180 and its associated components constitute the delay circuit18 of FIG. 1. As mentioned above, delay circuit 18 may be by-passed whenonly initial pulse amplitude measurement is desired.

Both the data input "D" and the preset input "Pre" of flip-flop 200 areconnected to a positive output provided by power supply 500. The Qoutput of flip-flop 200 is connected to the anode of diode D₄, thecathode of which is connected to the clear input "Clr" of flip-flop 200.Resistor R₁₂ is connected parallel to D₄. The clear input "Clr" isconnected also to one side of a capacitor C₄, the other side of which isgrounded. The Q output of flip-flop 200 is connected to capacitor C₅.The other side of C₅ is connected through resistor R₁₃ to ground. Thejunction of C₅ and R₁₃ is connected to the anode of diode D₅, thecathode of which is connected to a point 90. Point 90 is connectedthrough resistor R₁₄ to ground.

Similarly, the Q output of flip-flop 200 is connected to capacitor C₆,the other side of which is connected through resistor R₁₅ to ground. Thejunction of C₆ and R₁₅ is connected to the anode of diode D₆, thecathode of which is connected to point 90.

Point 90 is connected to the clock input "C" of the "hold" flip-flop220, the data input "D" and the preset input "Pre" of which areconnected to the positive output of power supply 500. The Q output offlip-flop 220 is connected to the anode of diode D₇, the cathode ofwhich is connected to the clear input "Clr" of flip-flop 220. ResistorR₁₆ is connected parallel to diode D₈. A capacitor C₇ is grounded at oneside, and connected at the other side to the clear input "Clr" offlip-flop 220. The Q output of flip-flop 220 is connected to the datainput "D" of delay flip-flop 180 and to the cathode of diode D₈, theanode of which is connected to hold output 24.

An "autohold" flip-flop 240 has its clock input "C" connected to the Qoutput of timer flip-flop 200. Both the preset input "Pre" and the datainput "D" of autohold flip-flop 240 are connected to the positive outputof power supply 500. The Q output of flip-flop 240 is connected to thecathode of a diode D₉, the anode of which is connected to one contact ofa single-pole single-throw switch S₄ used to activate the "autohold"circuit. The second contact of S₄ is connected to hold output terminal24. The clear input "Clr" of flip-flop 240 is connected through resistorR₁₇ to the positive output of power supply 500. Also, the clear input"Clr" is connected to one contact of momentary contact reset switch S₅,the other side of which is grounded.

The Q output of timer flip-flop 200 is connected to the anode of a diodeD₁₀, the cathode of which is connected to the gate of FET Q₁.

FIG. 3(b) shows a power supply 500 suitable for use with the circuit ofFIG. 3(a). Preferably the power supply used will operate from a single 9volt dry cell, so the unit will be wholly portable. Power supply 500provides positive and negative outputs of ±4.5 volts.

Component values which have been found to be suitable for the circuit ofFIG. 3(a) are provided in the following list:

    ______________________________________                                        R.sub.1 976.KΩ R.sub.10   22.MΩ                                   R.sub.2 24.9KΩ R.sub.11   2.MΩ                                    R.sub.3 1.KΩ   R.sub.12 -R.sub.17                                                                       22.MΩ                                   R.sub.4 249.KΩ R.sub.18   1.13MΩ                                  R.sub.5 1.MΩ   R.sub.19   11.5MΩ                                  R.sub.6 88.MΩ  R.sub.20   7.32MΩ                                  R.sub.7 48.7KΩ R.sub.21   7.32Ω                                   R.sub.8 22.MΩ  R.sub.22   22.MΩ                                   R.sub.9 1.MΩ                                                            C.sub.1 .18μf     C.sub.7    .0056μf                                    C.sub.2 470.pf       C.sub.8    .018μf                                     C.sub.3 .18μf     C.sub.9    .018μf                                     C.sub.4 .082μf    C.sub.10   6.9μf                                      C.sub.5 .0047μf   C.sub.11   6.8μf                                      C.sub.6 .0047μf                                                            ______________________________________                                    

D₁ -d₉ 1n914 type

A₁ -a₄ 776 type

Q₁ p 1087e p-channel FET

The circuit of FIG. 3(a) operates as follows. Unity gain amplifier A₁provides current amplification for the attenuated input signal andapplies it to capacitor C₁ through normally conducting FET Q₁ to chargecapacitor C₁ to the signal voltage. Amplifier A₂ amplifies the signal oncapacitor C₁ and applies it to output terminal 14. Resistances R₁, R₂,R₄ and R₅ are preselected so that the voltage at output 14 is attenuatedby a factor of 10 from the input signal. This enables the track and holdsystem to operate on a wider range of signals while using a single 9volt dry cell. Conveniently, resistors R₁₈ and R₁₉ are preselected sothat the voltage at output 16 is attenuated by a factor of 1000 from theinput signal, so that a millivolt scale can be used on an associatedmeter to provide full voltage readings.

The leading edge of a pulse at the output 60 of amplifier A₂ is detectedby the AC pulse amplifier including trigger amplifier A₃. The designparameters, including amplification factor and the size of inputcapacitor C₂, taken in conjunction with the trigger threshold voltage offlip-flop 180 or 200, determine what input risetime characteristicsconstitute a pulse. The position of trigger polarity switch S₂determines whether the AC amplifier incorporating amplifier A₃ willproduce a positive output at the anode of diode D₂ for a positive inputsignal at amplifier A₂ or whether the positive A₃ output will beproduced for a negative signal at amplifier A₂. Switch S₂ is manuallyselectable in the illustrated embodiment of the invention. Diode D₂passes unipolar positive pulses to the clock input of flip-flop 180 or200, depending on the position of S₃. Diode D₂ reduces the stress on theflip-flop by excluding negative pulses, and the diode drop maximizes thepositive baseline conditions while maintaining proper circuit operation.The values given for this illustrative embodiment will produce anappropriate activation signal for a one volt input signal excursion atinput 10 with a risetime faster than 2 milliseconds.

The operation of the delay timing circuit including flip-flop 180proceeds as follows. Initially the clock input C is low and the datainput D is high, the Q output and the clear input "Clr" are also high.When a positive pulse is applied to the clock input C, the flip-flop 180stores the D value as Q so that Q becomes high and Q goes low. Thiscondition presists even after the positive input at C has disappeared.When Q goes low, capacitor C₃ is gradually discharged through selectableresistance R₁₁. At some time the voltage applied to the clear input bycapacitor C₃ causes Q to reset to the zero or low state and Q to changeto the high state, and the circuit can then be retriggered. This timemay be read from the scale surrounding the R₁₁ potentiometer shaft.Diode D₃ reduces the retrigger set up time by quickly charging C₃.

In the position shown in FIG. 3(a), by-pass switch S₃ connects the Qoutput of flip-flop 180 to the clock input "C" of timer flip-flop 200.The low to high return of the Q output of flip-flop 180 clocks flip-flop200. Since "D" and "Pre" are both high, the Q output goes high and the Qoutput goes low. As a first consequence, FET Q₁ is turned off anddisconnects capacitor C₁ from any new input signals. Thus, while the Qoutput of timer flip-flop 200 remains high the signal applied to outputterminal 14 is determined by the potential stored on capacitor C₁ whichis representative of the pulse amplitude after the delay period causedby delay flip-flop 180.

Also, when timer flip-flop 200 is clocked, the voltage rise at its Qoutput is coupled through capacitor C₆ and diode D₆ to clock holdflip-flop 220. Hence, the Q output of flip-flop 220 goes low, causingthe normally high output at 24 to go low. The duration of this holdcommand is set by the discharge time of capacitor C₇ through resistorR₁₆, illustratively 200 milliseconds.

Flip-flop 200 functions like delay flip-flop 180 and after a timeillustratively 1500 milliseconds the voltage applied to the clear inputby capacitor C₄ causes its Q output thereof to return to low, and,correspondingly, its Q output to return to high. One consequence of thisis the FET Q₁ will close (turn on), so that new input signals can passto C₁. Another consequence is that the transition of Q from low to highcauses point 90 to go high again. Since the Q output is coupled throughcapacitor C₅ and diode D₅ to the clock input of hold flip-flop 220, thevoltage rise again clocks flip-flop 220. Hence, a second "hold" commandfor 200 milliseconds is applied to hold output 24, as described above.

The Q output of flip-flop 220 is connected to the "D" of flip-flop 180.If the data input D is held in the low state, the presence of a positivepulse at C does not cause the delay circuit to operate. Hence, flip-flop180 is disabled for the duration of the hold command, so that timerflip-flop 200 cannot be clocked during that hold command. As a result,intermediate characteristics of pulses reaching trigger amplifier A₃when the FET Q₁ is closed can not open the FET even if A₃ is triggered.

Finally, an autohold flip-flop 240 is engaged when switch S₄ is closed.The return of the Q output of timer flip-flop 200 from low to high willclock flip-flop 240, providing an open-end hold command at output 24until switch S₅ is closed to ground the clear input.

It will be appreciated that the track and hold circuit of presentinvention achieves the aforementioned objectives and provides anextremely useful result. This track and hold circuit used in conjunctionwith a multimeter is fully capable of measuring pulse amplitude at anyposition on a pulse, as well as pulse duration. Moreover as a result oftaking the trigger after the storage device, filtering against noisesources is achieved for reliable operation.

It will be apparent to those skilled in the art that variousmodifications of the present invention are possible. For example,modifications to the trigger amplifier can be made to accommodate a widerange of pulse recognition or level change conditions. The functions ofthe delay and timer circuits could be implemented by more conventionalsingle shot multivibrator integrated circuits. However, the embodimentshown herein provides very low power consumption, an important featurefor portable, battery-powered devices.

What is claimed is:
 1. A track and hold circuit comprising:input meansfor receiving an input signal; a storage device for receiving a signalfrom said input means and for storing a signal corresponding to theamplitude of said input signal; output means coupled to said storagedevice; a pulse detector for detecting a leading edge of a pulse passingfrom said storage device to said output means; a switch responsive tosaid detector for isolating said storage device from signals applied tosaid input means and a delay circuit responsive to said detector forinterposing a delay of selectable duration prior to switching saidswitch.
 2. The system according to claim 1 further comprising a timercircuit responsive to said detector for activating said switch for afirst predetermined period.
 3. The system according to claim 1 whereinsaid storage device includes a non-polar capacitor.
 4. The systemaccording to claim 1 wherein said delay circuit includesa D-typeflip-flop, a capacitor connected between the clear input of saidflip-flop and a reference potential, the side of said capacitorconnected to said "clear" input being connected also to the Q output ofsaid flip-flop, whereby after said flip-flop is clocked, said capacitordischarges to said reference and activates said clear input to resetsaid flip-flop.
 5. The system according to claim 1 wherein said delaycircuit includes a one shot multivibrator.
 6. The system according toclaim 2 further comprising a hold circuit responsive to said timer forproviding hold commands to a "hold" output of said system, said holdcommand enduring for a second predetermined period when said switchopens and when said switch closes.
 7. The system according to claim 6wherein said hold circuit also communicates with said delay circuit todisable said delay circuit for a third predetermined period beginningwith the end of said first predetermined period.
 8. The system accordingto claim 1 further comprising switch means connected to said pulsedetector for selecting the polarity of a leading edge to which saidpulse detector responds.
 9. The system according to claim 8 wherein saidpulse detector includes an operational amplifier and wherein saidpolarity switch means connects said storage device to a selected one ofthe inverting and non-inverting inputs of said amplifier and connects areference potential to the other one of said inputs.
 10. The systemaccording to claim 1 wherein said switch comprises a field effecttransistor coupling said input means with said storage device, saidtransistor having a control gate, coupled to said pulse detector, forreceiving signals for opening and closing said switch.
 11. The systemaccording to claim 1 wherein said pulse detector includes an AC pulseamplifier connected to receive signals from said output means andsensitive to the rate of change of said signals and operating to supplyan activation signal to said delay circuit.
 12. A circuit for providingsignals to determine the amplitude and width of a pulse applied to itsinput comprising:an input circuit; storage means for storing a signalcorresponding to the instantaneous value of the amplitude of the pulseapplied to said input circuit; means for detecting the leading edge ofsaid pulse; variable delay means for disconnecting said storage meansfrom said input circuit a selected time after the detection of theleading edge of said pulse; said storage means including means forretaining the value of the signal stored therein at the time of beingdisconnected from said input circuit; and means for varying the delay ofsuch variable delay means for allowing measurement of the amplitude ofthe pulse at various points after a leading edge.
 13. A circuitaccording to claim 12 wherein said storage means includes a bufferamplifier having a low output impedance and a capacitor coupled at oneside to the output of said buffer amplifier and coupled at the otherside to ground.
 14. A circuit according to claim 13 further comprisingan output amplifier having an input coupled to the ungrounded side ofsaid capacitor and having an output coupled to an output terminal.
 15. Acircuit according to claim 14 including a voltage divider networkcoupled to a selected one of said input circuit and the output of saidoutput amplifier for attenuating by a factor of 1,000 the signal at saidoutput terminal from the signal applied to said input circuit.
 16. Acircuit according to claim 14 wherein said means for detecting theleading edge of said pulse includes an AC pulse amplifier having onegrounded input and another input coupled to the output of said outputamplifier, said pulse amplifier producing an activation signal inresponse to a predetermined risetime of a signal applied thereto.